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integrated circuit systems, inc. general description features ics9248-20 0276e?12/15/08 block diagram pentium/pro tm system clock chip pin configuration 48-pin ssop generates system clocks for cpu, ioapic, pci, plus 14.314 mhz ref (0:2), usb, and super i/o supports single or dual processor systems supports spread spectrum modulation for cpu & pci clocks, down spread -0.5% skew from cpu (earlier) to pci clock (rising edges for 100/33.3mhz) 1.5 to 4ns two fixed outputs at 48mhz. separate 2.5v and 3.3v supply pins 2.5v or 3.3v output: cpu, ioapic 3.3v outputs: pci, ref, 48mhz no power supply sequence requirements uses external 14.318mhz crystal, no external load cap required for c l =18pf crystal 48 pin 300 mil ssop the ics9248-20 is a clock synthesizer chip for pentium and pentiumpro cpu based desktop/notebook systems that will provide all necessary clock timing. features include four cpu and eight pci clocks. three reference outputs are available equal to the crystal frequency. additionally, the device meets the pentium power-up stabilization requirement, assuring that cpu and pci clocks are stable within 2ms after power-up. pd# pin enables low power mode by stopping crystal osc and pll stages. other power management features include cpu_stop#, which stops cpu (0:3) clocks, and pci_stop#, which stops pciclk (0:6) clocks. high drive cpuclk outputs typically provide greater than 1 v/ns slew rate into 20pf loads. pciclk outputs typically provide better than 1v/ns slew rate into 30pf loads while maintaining 505% duty cycle. the ref clock outputs typically provide better than 0.5v/ns slew rates. the ics9248-20 accepts a 14.318mhz reference crystal or clock as its input and runs on a 3.3v core supply. power groups vdd = supply for pll core vdd1 = ref (0:2), x1, x2 vdd2 = pciclk_f, pciclk (0:6) vdd3 = 48mhz0, 48mhz1 vddl1 = ioapic (0:1) vddl2 = cpuclk (0:3) ground groups gnd = ground for pll core gnd1 = ref (0:2), x1, x2 gnd2 = pciclk_f, pciclk (0:6) gnd3 = 48mhz0, 48mhz1 gndl1 = ioapic (0:1) gndl2 = cpuclk (0:3)
2 ics9248-20 0276e?12/15/08 pin descriptions select functions notes: 1. tclk is a test clock driven on the x1 (crystal in pin) input during test mode. 2. -0.5% modulation down spread from the selected frequency. y t i l a n o i t c n u fu p c , i c p f _ i c p f e rc i p a o i z h m 8 4 n o i t c e l e s e t a t s i r tz - i hz - i hz - i hz - i hz - i h e d o m t s e t2 / k l c t 1 6 / k l c t 1 k l c t 1 k l c t 1 2 / k l c t 1 m u r t c e p s d a e r p sd e t a l u d o m 2 d e t a l u d o m 2 z h m 8 1 3 . 4 1z h m 8 1 3 . 4 1z h m 0 . 8 4 l e s # 6 6 / 0 0 1 1 s f0 s fn o i t c n u f 000 e t a t s - i r t 001 ) d e v r e s e r ( 010 ) d e v r e s e r ( 011 3 . 3 3 , u p c z h m 6 . 6 6 e v i t c a i c p 100 e d o m t s e t 101 ) d e v r e s e r ( 110 ) d e v r e s e r ( 111 3 . 3 3 , u p c z h m 0 0 1 e v i t c a i c p r e b m u n n i pe m a n n i pe p y tn o i t p i r c s e d 7 4 , 2 , 1) 2 : 0 ( f e rt u ot u p t u o k c o l c z h m 8 1 3 . 4 1 31 d n gr w ps t u p t u o f e r r o f d n u o r g 41 xn i p a c d a o l f p 3 3 l a n r e t n i s a h , t u p n i l a t s y r c z h m 8 1 3 . 4 1 n i _ l a t x 2 x m o r f r o t s i s e r k c a b d e e f d n a 52 xt u of p 3 3 p a c d a o l l a n r e t n i s a h , t u p t u o l a t s y r c t u o _ l a t x 8 1 , 2 1 , 62 d n gr w ps t u p t u o i c p r o f d n u o r g 7f _ k l c i c pt u ot u p t u o i c p g n i n n u r e e r f 7 1 , 6 1 , 4 1 , 3 1 , 1 1 , 0 1 , 8) 6 : 0 ( k l c i c pt u ov 3 . 3 e l b i t a p m o c l t t . s t u p t u o k c o l c i c p 5 1 , 92 d d vr w pv 3 . 3 y l l a n i m o n , s t u p t u o k l c i c p r o f r e w o p 3 3 , 9 1d d vr w pv 3 . 3 y l l a n i m o n , e r o c r o f r e w o p d e t a l o s i 2 3 , 0 2d n gr w pe r o c r o f d n u o r g d e t a l o s i 1 23 d d vr w pv 3 . 3 y l l a n i m o n , s t u p t u o z h m 8 4 r o f r e w o p 3 2 , 2 2) 1 : 0 ( z h m 8 4t u os t u p t u o z h m 8 4 4 23 d n gr w ps t u p t u o z h m 8 4 r o f d n u o r g 5 2# 6 . 6 6 / 0 0 1 l e sn i z h m 6 . 6 6 r o z h m 0 0 1 g n i l b a n e r o f n i p t c e l e s ) z h m 3 . 3 3 s u o n o r h c n y s s y a w l a i c p ( z h m 6 . 6 6 = l , z h m 0 0 1 = h 7 2 , 6 2) 1 : 0 ( s fn is n i p t c e l e s y c n e u q e r f 8 2# d a e r p sn iw o l n e h w e r u t a e f m u r t c e p s d a e r p s s e l b a n e 9 2# d pn iw o l e v i t c a , p i h c n w o d s r e w o p 0 3# p o t s _ u p cn iw o l n e h w l e v e l " 0 " c i g o l t a s k c o l c u p c s t l a h 1 3# p o t s _ i c pn iw o l n e h w l e v e l " 0 " c i g o l t a s u b i c p s t l a h 1 4 , 7 32 l d d vr w pv 5 . 2 y l l a n i m o n , s t u p t u o u p c r o f r e w o p 8 3 , 4 32 l d n gr w p. s t u p t u o u p c r o f d n u o r g 0 4 , 9 3 , 6 3 , 5 3) 0 : 3 ( k l c u p ct u ov 5 . 2 @ s t u p t u o k c o l c t s o h d n a u p c 2 4c / n- d e t c e n n o c y l l a n r e t n i t o n 3 41 l d n gr w ps t u p t u o c i p a o i r o f d n u o r g 5 4 , 4 4) 1 : 0 ( c i p a o it u ov 5 . 2 @ ) z h m 8 1 3 . 4 1 ( s t u p t u o c i p a o i 6 41 l d d vr w pv 5 . 2 y l l a n i m o n , s t u p t u o c i p a o i r o f r e w o p 8 41 d d vr w pv 3 . 3 l a n i m o n , 2 x , 1 x , ) 2 : 0 ( f e r r o f y l p p u s
3 ics9248-20 0276e?12/15/08 technical pin function descriptions vdd(1,2,3) this is the power supply to the internal core logic of the device as well as the clock output buffers for ref(0:2), pciclk_f, pciclk (0:6), 48mhz0, 48mhz1. this pin operates at 3.3v volts. clocks from the listed buffers that it supplies will have a voltage swing from ground to this level. for the actual guaranteed high and low voltage levels for the clocks, please consult the dc parameter table in this data sheet. vddl1,2 this is the power supply for the cpuclk (0:3) and ioapic output buffers. the voltage level for these outputs may be 2.5 or 3.3volts. clocks from the buffers that each supplies will have a voltage swing from ground to this level. for the actual guaranteed high and low voltage levels of these clocks, please consult the dc parameter table in this data sheet. gnd (1,2,3) this is the ground to the internal core logic of the device as well as the clock output buffers for ref(0:2), pciclk_f, pciclk (0:6), 48mhz 0, 48mhz1. gndl (1,2) this is the ground for the cpuclk (0:3) and ioapic output buffers. x1 this input pin serves one of two functions. when the device is used with a crystal, x1 acts as the input pin for the reference signal that comes from the discrete crystal. when the device is driven by an external clock signal, x1 is the device input pin for that reference clock. this pin also implements an internal crystal loading capacitor that is connected to ground. with a nominal value of 33pf no external load cap is needed for a c l =17 to 18pf crystal. x2 this output pin is used only when the device uses a crystal as the reference frequency source. in this mode of operation, x2 is an output signal that drives (or excites) the discrete crystal. the x2 pin will also implement an internal crystal loading capacitor nominally 33pf. cpuclk (0:3) these output pins are the clock outputs that drive processor and other cpu related circuitry that requires clocks which are in tight skew tolerance with the cpu clock. the voltage swing of these clocks is controlled by the voltage level applied to the vddl2 pin of the device. see the functionality table for a list of the specific frequencies that are available for these clocks and the selection codes to produce them. 48mhz (0:1) this is a fixed frequency clock output that is typically used to drive super i/o devices. outputs 0 and 1 are defined as 48mhz. ioapic (0:1) this output is a fixed frequency output clock that runs at the reference input (typically 14.31818mhz) . its voltage level swing is controlled by vddl1 and may operate at 2.5 or 3.3volts. ref(0:2) the ref outputs are fixed frequency clocks that run at the same frequency as the input reference clock x1 or the crystal (typically 14.31818mhz) attached across x1 and x2. pciclk_f this output is equal to pciclk(0:6) and is free running, and will not be stopped by pci_stop#. pciclk (0:6) these output clocks generate all the pci timing requirements for a pentium/pro based system. they conform to the current pci specification. they run at 33.3 mhz. select 100/66.6mhz# this input pin controls the frequency of the clocks at the cpuclk, pciclk and sdram output pins. if a logic ?1? value is present on this pin, the 100mhz clock will be selected. if a logic ?0? is used, the 66.6mhz frequency will be selected. the pci clock is multiplexed to be 33.3mhz for both select cases. pci is synchronous at the rising edge of pci to the cpu rising edge (with the skew making cpu early). pwr_dwn# this is an asynchronous active low input pin used to power down the device into a low power state by not removing the power supply. the internal clocks are disabled and the vco and crystal are stopped. powered down will also place all the outputs in a low state at the end of their current cycle. the latency of power down will not be greater than 3ms. cpu_stop# this is a synchronous active low input pin used to stop the cpuclk clocks in an active low state. all other clocks including sdram clocks will continue to run while this function is enabled. the cpuclk?s will have a turn on latency of at least 3 cpu clocks. pci_stop# this is a synchronous active low input pin used to stop the pciclk clocks in an active low state. it will not affect pciclk_f nor any other outputs.
4 ics9248-20 0276e?12/15/08 power management ics9248-20 power management requirements clock enable configuration full clock cycle timing is guaranteed at all times after the system has initially powered up except where noted. during power up and power down operations using the pd# select pin will not cause clocks of a shorter or longer pulse than that of the running clock. the first clock pulse coming out of a stopped clock condition may be slightly distorted due to clock network charging circuitry. board routing and signal loading may have a large impact on the initial clock distortion also. notes. 1. clock on latency is defined from when the clock enable goes active to when the first valid clock comes out of the device. 2. clock off latency is defined from when the clock enable goes inactive to when the last clock is driven low out of the device . 3. power up latency is when pd# goes inactive (high) to when the first valid clocks are output by the device. 4. power down has controlled clock counts applicable to cpuclk, pciclk only. the ref and ioapic will be stopped independent of these. l a n g i se t a t s l a n g i s y c n e t a l e e r f f o s e g d e g n i s i r f o . o n k l c i c p g n i n n u r # p o t s _ u p c) d e l b a s i d ( 0 2 1 ) d e l b a n e ( 1 1 1 # p o t s _ i c p) d e l b a s i d ( 0 2 1 ) d e l b a n e ( 1 1 1 # d p l a m r o n ( 1 ) n o i t a r e p o 3 s m 3 ) n w o d r e w o p ( 0 4 x a m 2 # p o t s _ u p c# p o t s _ i c p# n w d _ r w pk l c u p ck l c i c p , s k c o l c r e h t o , s c i p a o i , f e r 0 z h m 8 4 1 z h m 8 4 l a t s y r cs o c v xx0w o lw o ld e p p o t sf f of f o 001w o lw o lg n i n n u rg n i n n u rg n i n n u r 011w o lz h m 3 . 3 3g n i n n u rg n i n n u rg n i n n u r 101 - m 6 . 6 6 / 0 0 1 z h w o lg n i n n u rg n i n n u rg n i n n u r 111 - m 6 . 6 6 / 0 0 1 z h z h m 3 . 3 3g n i n n u rg n i n n u rg n i n n u r
5 ics9248-20 0276e?12/15/08 pci_stop# timing diagram pci_stop# is an asynchronous input to the ics9248-20 . it is used to turn off the pciclk (0:6) clocks for low power operation. pci_stop# is synchronized by the ics9248-20 internally. the minimum that the pciclk (0:6) clocks are enabled (pci_stop# high pulse) is at least 10 pciclk (0:6) clocks. pciclk (0:6) clocks are stopped in a low state and started with a full high pulse width guaranteed. pciclk (0:6) clock on latency cycles are only one rising pciclk. clock off latency is one pciclk clock. cpu_stop# timing diagram cpustop# is an asychronous input to the clock synthesizer. it is used to turn off the cpuclks for low power operation. cpu_stop# is synchronized by the ics9248-20 . the minimum that the cpuclk is enabled (cpu_stop# high pulse) is 100 cpuclks. all other clocks will continue to run while the cpuclks are disabled. the cpuclks will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. cpuclk on latency is less than 4 cpuclks and cpuclk off latency is less than 4 cpuclks. notes: 1. all timing is referenced to the internal cpuclk. 2. cpu_stop# is an asynchronous input and metastable conditions may exist. this signal is synchronized to the cpuclks inside the ics9248-20 . 3. all other clocks continue to run undisturbed. 4. pd# and pci_stop# are shown in a high (true) state. notes: 1. all timing is referenced to the internal cpuclk (defined as inside the ics9148 device.) 2. pci_stop# is an asynchronous input, and metastable conditions may exist. this signal is required to be synchronized inside the ics9248-20. 3. all other clocks continue to run undisturbed. 4. pd# and cpu_stop# are shown in a high (true) state.
6 ics9248-20 0276e?12/15/08 pd# timing diagram the power down selection is used to put the part into a very low power state without turning off the power to the part. pd# is an asynchronous active low input. this signal is synchronized internally by the ics9248-20 prior to its control action of powering down the clock synthesizer. internal clocks will not be running after the device is put in power down state. when pd# is active (low) all clocks are driven to a low state and held prior to turning off the vcos and the crystal oscillator. the power on latency is guaranteed to be less than 3ms. the power down latency is less than three cpuclk cycles. pci_stop# and cpu_stop# are don?t care signals during the power down operations. notes: 1. all timing is referenced to the internal cpuclk (defined as inside the ics9148 device). 2. pd# is an asynchronous input and metastable conditions may exist. this signal is synchronized inside the ics9148. 3. the shaded sections on the vco and the crystal signals indicate an active clock is being generated.
7 ics9248-20 0276e?12/15/08 absolute maximum ratings supply voltage . . . . . . . . . . . . . . . . . . . . . . . 7.0 v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . gnd ?0.5 v to v dd +0.5 v ambient operating temperature . . . . . . . . . . 0c to +70c storage temperature . . . . . . . . . . . . . . . . . . . ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. electrical characteristics - input/supply/common output parameters t a = 0 - 70c; supply voltage v dd = v ddl = 3.3 v +/-5% (unless otherwise stated) parameter symbol c onditions min typ max units input high voltage v ih 2v dd +0.3 v input low voltage v il v ss -0.3 0.8 v input high current i ih v in = v dd 0.1 5 ma input low current i il1 v in = 0 v; inputs with no pull-up resistors -5 2.0 ma input low current i il2 v in = 0 v; inputs with pull-up resistors -200 -100 ma operating i dd3.3op66 c l = 0 pf; select @ 66mhz 60 170 ma supply current i dd3.3op100 c l = 0 pf; select @ 100mhz 66 170 ma power down i dd3.3pd c l = 0 pf; with input address to vdd or gnd 70 600 ma supply current input frequency f i v dd = 3.3 v; 11 14.318 16 mhz c in logic inputs 5 pf c inx x1 & x2 pins 27 36 45 pf transition time 1 t trans to 1st crossing of target freq. 3 ms settling time 1 t s from 1st crossing to 1% target freq. 5 ms clk stabilization 1 t stab from v dd = 3.3 v to 1% target freq. 3 ms skew 1 t cpu-pci1 v t = 1.5 v; 1.5 3 4 ns 1 guaranteed by design, not 100% tested in production. input capacitance 1 electrical characteristics - input/supply/common output parameters t a = 0 - 70c; supply voltage v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5% (unless otherwise stated) parameter symbol conditions min typ max units operating i dd2.5op66 c l = 0 pf; select @ 66.8 mhz 16 72 ma supply current i dd2.5op100 c l = 0 pf; select @ 100 mhz 23 100 ma skew 1 t cpu-pci2 v t = 1.5 v; v tl = 1.25 v 1.5 3 4 ns 1 guaranteed by design, not 100% tested in production.
8 ics9248-20 0276e?12/15/08 electrical characteristics - cpuclk t a = 0 - 70c; v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5%; c l = 10 - 20 pf (unless otherwise stated) parameter symbol conditions min typ max units output high voltage v oh2 b i oh = -12.0 ma 2 2.3 v output low voltage v ol2 b i ol = 12 ma 0.2 0.4 v output high current i oh2 b v oh = 1.7 v -41 -19 ma output low current i ol2 b v ol = 0.7 v 19 37 ma rise time t r2b 1 v ol = 0.4 v, v oh = 2.0 v 1.25 1.6 ns fall time t f2b 1 v oh = 2.0 v, v ol = 0.4 v 1 1.6 ns duty cycle d t2b 1 v t = 1.25 v 454855% skew t sk2b 1 v t = 1.25 v 30 175 ps jitter, cycle-to-cycle t jcyc-cyc2b 1 v t = 1.25 v 150 200 ps jitter, one sigma t j1s2b 1 v t = 1.25 v 40 150 ps jitter, absolute t jabs2b 1 v t = 1.25 v -250 140 +250 ps 1 guaranteed by design, not 100% tested in production. electrical characteristics - ioapic t a = 0 - 70c; v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5%; c l = 20 pf parameter symbol c onditions min typ max units output high voltage v oh4 b i oh = -18 ma 2 2.2 v output low voltage v ol4 b i ol = 18 ma 0.33 0.4 v output high current i oh4b v oh = 1.7 v -41 -28 ma output low current i ol4b v ol = 0.7 v 29 37 ma rise time 1 t r4b v ol = 0.4 v, v oh = 2.0 v 1.4 1.6 ns fall time 1 t f4b v oh = 2.0 v, v ol = 0.4 v 1.3 1.6 ns duty cycle 1 d t4b v t = 1.25 v 45 54 55 % skew 1 t sk4b 1 v t = 1.25 v 60 250 ps jitter, one sigma 1 t j1s4b v t = 1.25 v 1 3 % jitter, absolute 1 t jabs4b v t = 1.25 v -5 5 % 1 guaranteed by design, not 100% tested in production.
9 ics9248-20 0276e?12/15/08 electrical characteristics - pciclk t a = 0 - 70c; v dd = v ddl = 3.3 v +/-5%; c l = 30 pf parameter symbol c onditions min typ max units output high voltage v oh1 i oh = -11 ma 2.4 3.1 v output low voltage v ol1 i ol = 9.4 ma 0.1 0.4 v output high current i oh1 v oh = 2.0 v -62 -22 ma output low current i ol1 v ol = 0.8 v 16 57 ma rise time 1 t r1 v ol = 0.4 v, v oh = 2.4 v 1.5 2 ns fall time 1 t f1 v oh = 2.4 v, v ol = 0.4 v 1.1 2 ns duty cycle 1 d t1 v t = 1.5 v 45 50 55 % skew 1 t sk1 v t = 1.5 v 140 250 ps jitter, one sigma 1 t j1s1 v t = 1.5 v 17 150 ps jitter, absolute 1 t jabs1 v t = 1.5 v -500 70 500 ps 1 guaranteed by design, not 100% tested in production. electrical characteristics - ref t a = 0 - 70c; v dd = v ddl = 3.3 v +/-5%; c l = 10 - 20 pf (unless otherwise stated) parameter symbol conditions min typ max units output high voltage v oh5 i oh = -12 ma 2.6 3.1 v output low voltage v ol5 i ol = 9 ma 0.17 0.4 v output high current i oh5 v oh = 2.0 v -44 -22 ma output low current i ol5 v ol = 0.8 v 29 42 ma rise time 1 t r5 v ol = 0.4 v, v oh = 2.4 v 1.4 2 ns fall time 1 t f5 v oh = 2.4 v, v ol = 0.4 v 1.1 2 ns duty cycle 1 d t5 v t = 1.5 v 455355% jitter, one sigma 1 t j1s5 v t = 1.5 v 1 3 % jitter, absolute 1 t jabs5 v t = 1.5 v 35% 1 guaranteed by design, not 100% tested in production.
10 ics9248-20 0276e?12/15/08 electrical characteristics - 48 mhz t a = 0 - 70c; v dd = v ddl = 3.3 v +/-5%; c l = 10 - 20 pf (unless otherwise stated) parameter symbol conditions min typ max units frequency accuracy 1 f acc4 8 m 167 ppm output high voltage v oh5 i oh = -12 ma 2.6 3 v output low voltage v ol5 i ol = 9 ma 0.14 0.4 v output high current i oh5 v oh = 2.0 v -44 -22 ma output low current i ol5 v ol = 0.8 v 16 42 ma rise time 1 t r5 v ol = 0.4 v, v oh = 2.4 v 1.2 4 ns fall time 1 t f5 v oh = 2.4 v, v ol = 0.4 v 1.2 4 ns duty cycle 1 d t5 v t = 1.5 v 455255% jitter, one sigma 1 t j1s5 v t = 1.5 v 1 3 % jitter, absolute 1 t jabs5 v t = 1.5 v 35% 1 guaranteed by design, not 100% tested in production.
11 ics9248-20 0276e?12/15/08 ordering information ics9248 y f-20lf this table in inches example: lead free , rohs compliant (optional) designation for tape and reel packaging package type f = ssop revision designator (will not correlate with datasheet revision) device type prefix ics = standard device ics xxxx y f - t lf minmaxminmax a 2.41 2.80 .095 .110 a1 0.20 0.40 .008 .016 b 0.20 0.34 .008 .0135 c 0.13 0.25 .005 .010 d e 10.03 10.68 .395 .420 e1 7.40 7.60 .291 .299 e h 0.38 0.64 .015 .025 l 0.50 1.02 .020 .040 n a 0808 variations minmaxminmax 48 15.75 16.00 .620 .630 10-0034 0.635 basic 0.025 basic common dimensions in millimeters in inches common dimensions reference doc.: jedec publication 95, mo-118 300 mil ssop n see variations see variations d mm. d (inch) symbol see variations see variations
12 ics9248-20 0276e?12/15/08 revision history rev. issue date description page # d 6/4/2007 updated package and ordering information. 11 e 12/15/2008 removed ics prefix from ordering information. 11

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